TWSDAC-LT The Well Segmented DAC (Lite) bundle

24 bit 384kHz discrete DAC

The TWSDAC-LT-BNDL is the 384 kHz DAC Lite bundle. The bundle includes the following

  1. TWTMC-DRIXO 11.2896 MHz oscillator finished board with crystal
  2. TWTMC-DRIXO 12.288 MHz oscillator finished board with crystal
  3. TWSAFB-LT FIFO buffer finished board
  4. TWSAFB-UI User interface finished board
  5. TWSDAC-LT segmented R2R DAC Lite finished board
  6. TWRPS-UGL low noise power supply for oscillators finished board
  7. TWRPS-LT-TB transformers bank bare board
  8. TWRPS-LT low noise power supply for FIFO buffer finished board
  9. TWRPS-TS low noise power supply for DAC Lite finished board

See the User Manual of each board for specifications and connections.

The following items has to be sourced to complete the DAC:

  • through hole components to populate the TWRPS-LT-TB transformers bank
  • enclosures for DAC (1) and oscillators (2)
  • SMA terminated coaxial cables to connect oscillators with FIFO buffer


Input format: I2S
Inputs: 4 x selectable inputs
Format: up to 24 bit 384kHz
Architecture: segmented thermometer (first 3 MSBs) / R2R discrete ladder with sign magnitude
notation and digital calibration
Clock mode: stopped clock
Master clock: 11.2896/12.288 MHz up to 352.8/384KHz
Calibration: the DAC is calibrated for maximum accuracy
Output: voltage output 1.4V rms
Configuration: all settings can be configured one time by USB connection to the Windows
Display: user interface to manage some function on the fly like source selection, dither,
enable/disable DAC calibration and to display current sample rate
Master Clock selection: T-switch configuration relay to select the sample rate family instead of
Optical isolation: MCK and LRCK optical isolated from the FPGA and the micro to avoid
interferences (BCK and DATA signals optically isolated DAC side)
External Master Clock: 11.2896/12.288 MHz TWTMC-DRIXO oscillators
No RF: micro controller in standby during listening (no RF interference at all)
Direct clock output: LRCK/MCK directly from the Master clock (optical isolation) instead of from
the FPGA
Phase noise: very low phase noise outputs (MCK, LRCK)
Power supply: low noise linear and shunt regulators (without transformers)
Note: all finished boards (without RCA connector and transformers)