The Well Segmented Digital to Analog Converter

24 bit 384kHz discrete DAC

The TWSDAC-LT is 24 bit 384kHz segmented/sign magnitude discrete DAC with digital calibration.


Inputs: 24 bit PCM custom protocol (provided by the TWSAFB-LT FIFO buffer)
Format: up to 24 bit 384kHz
Architecture: segmented thermometer (first 3 MSBs) / R2R discrete ladder with sign magnitude notation
Clock mode: stopped clock
Master clock: 5.6448/6.144 MHz up to 176.4/192 KHz, 11.2896/12.288 MHz up to 352.8/384KHz
Isolation: BCK and DATA signals optically isolated
Calibration: the DAC can be calibrated for maximum accuracy, the TWSAFB-LT FIFO buffer applies the necessary corrections
Output: voltage output 1.2V to 1.8V rms
Power supply: digital +/- 3.3VDC to +/- 5VDC 50 mA, analog Vref +/- 3.3VDC to +/- 5VDC 30 mA
Board size: 163 x 140 mm