The Well Audio
Unfortunately we have not yet found the time to test the DAM1021 upgrade, that’s the reason why we have not yet published the User Manual.
Configuration and architecture are very simple: we only save the switches/ladder part of the DAC, throwing out all the FPGA/micro/PLL section.
This way the saved part of the DAC will be driven directly by the FIFO Lite with its external oscillators.
Therefore I2S input signal will feed the FIFO Lite and no longer the DAM input.
Then the TWSADB-OIDAM board is connected via the 20 output connections per channel from the DAM1021 FPGA to the 595s installed on the DAM DAC (20 instead of 18 because there are also the OE pins of the shift registers).
The digital filtering implemented in the FPGA of the DAM will no longer work because the FPGA part of the DAM will be excluded.
Any upsampling should be done in software before feeding the FIFO Lite which accepts up to 24 bit/384kHz.
Using the FIFO Lite to feed the DAM DAC there is no need to manage the adaptive clocking, no PLL is needed because the FIFO buffer gets the DAC operating in a different time domain, fully isolated from the source.
In order to fit the little LDO regulator board, the onboard regulator has to be removed and replaced with the new board.
There is a switch on the little LDO board wich allows to swith between the stock DAM and the upgraded DAM. Therefore the upgrade is reversible.