Reply To: Strengths and shortcomings of a FIFO and Phase noise measurements

Forum Digital line Strengths and shortcomings of a FIFO and Phase noise measurements Reply To: Strengths and shortcomings of a FIFO and Phase noise measurements

#1721
The Well Audio
Participant

I2S input and output data from the FIFO Lite are optically isolated.
Moreover source (I2S input) and DAC (FIFO output) operate in different time domains.
There aren’t any path between the two time domains (ground and VCC).

I2S input is processed by the FPGA in the “dirty” time domain, while LRCK output comes directly from the master clock (by dividers), the “clean” time domain.
While the BCK coming from the FPGA is very jittery, the LRCK coming from the master clock is very clean, its close in phase noise is much better than the one of the Master clock.
Some PN measurements will be published soon.

This provides a good way to drive all the DACs which switch on the LRCK or MCK signal, like TDA1541A, AD1862, SABRE, TWSDAC-LT and also TWSDAC-DSD as soon as it’s ready.
All our DACs available on the website provide full optical isolation from the FPGA FIFO side.
We have designed the TWSAFB-OI to provide optical isolation even for other DACs which don’t provide such isolation.

For the DACs which switch on the BCK (like the PCM1704, PCM1794 and so on), we have designed the TWSAFB-OIR.
It isolates (optically) all the signals coming from the FPGA and performs the reclocking of them by the clean Master clock.

Thre is a simple reason to design the “top version” of the FIFO.
In all the above boards the optical isolation is performed in the same PCB layout. Although there aren’t common paths between the “dirty” and the “clean” sides of the board, the isolation is not perfect.
That’s the reason to design totally separated boards linked by optic fiber.
This way we implement a brick wall between the two time domains. Nothing can pass through the optic fiber.
So that the dirty FPGA part of the FIFO cannot affects the DAC in any way.
Of course, this way is much more complex and expensive than the FIFO Lite, and it will need 3-4 chassis.

Then, about the main AC, battery supply systems are another brick wall against the PSU noise.

Finally, we well know that PN is steady state measurement, but we believe that timing errors heavy affect digital to analog conversion.

Of course, anyone can judge the result by his own ears.
We have no other way to measure the results, fancy tools like the AP are pretty useless in our opinion.