Reply To: The Well synchronized asynchronous FIFO buffer – Slaved I2S reclocker

Forum Digital line The Well synchronized asynchronous FIFO buffer – Slaved I2S reclocker Reply To: The Well synchronized asynchronous FIFO buffer – Slaved I2S reclocker

#1815
Ivan
Participant

And the second question.

Seems like on your FIFO (TWSAFB-LT) there is no external xtal (clock) selection pin like it is realized on your separate TWTMC-STS-FSDO-S board. Is this means that I am forced to use another (separate) xtals/clocks for the I2S source as your FIFO is waiting for already formed I2S for proper clock freq recognition?

Some explanation of my existing working scheme. In my existing DAC I do use your DRIXO clocks for generating/creating of the I2S from the very beginning. It works this way:

BeagleBone Black (LAN-I2S endpoint, botic driver) sends the signal of 0 (44k) or 1 (48k) from the dedicated GPIO pins in accordance with the playing sampling rate (through my board with the isolator chip) to J7 header of your TWTMC-STS-FSDO-S. Your TWTMC-STS-FSDO-S switches between two clocks (45/49MHz) and sends the needed masterclock (through my board over the isolator chip) back to BBB. BBB creates the I2S from the incoming (correctly chosed) DRIXO masterclock and sends it to FIFO (and then to DAC).

What is my point? I do not like situation when the initial I2S is formed from the other xtals/clocks that are worse than your DRIXO clocks. Will be sad to lost a possibility of a single clocking scheme for the whole chain from I2S initiation till the DAC tacting itself.

My questions are relates to the upcoming order and I just want to be ready for your stuff will come some months later. Andrea what can you suggest in conjuction with the above described?

Thank you!
Ivan.