- This topic has 100 replies, 16 voices, and was last updated 6 months ago by
The Well Audio.
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The Well Audio
This topic is about FIFO buffer and re-clocker to be used between digital sources and DACs in order to mitigate the incoming jitter.
You can find the original thread on diyaudio.com at the following link
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Olivier
This forum is welcome, I wish it long life,
I reduced the value of the Fifo Lite buffer,After some time with a value of 2M I went to 130 kb,I had better results with 130kB,improvement of space between instruments.
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multiblitz
Interesting…I am not yet there to change parameters, but clocks at the moment…
So, currently it euns with Crystek 957 in sockets on board. My question (I guess to Andrea): What is the absolute minimum procedure needed to change now to the drixo or Exo (when I want to compare sound) ?
I would guesstimate:
– Powering off the fifo/dac and the drixo
– Pull the crystek for 22.x out (while the 24.x stays at the moment)
– Wire the Drixo to the Fifo
– connect the usb cable to the fifo and connect it to the pc with the setup software
– power on clock and fifo
– setup the dac with the new 5.x frequency with the software and save
– power off-on the fifo
Correct ?
Or does the Fifo finds the new frequency (going from 22.x to 5.x) automatically, so no PC-setup procedure needed ?
or whould the crystek clock even automatically be ignored when attaching the drixo cable ?
I do have the EXO as well ready to compare with Drixo (both on 5.x)…This I guess would be just wiring the other clock, but no changes in the Fifo software/ no setup procedure when going from drixo 5.x to exo 5.x, right ?
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The Well Audio
Correct, the FIFO does not recognize the different oscillator frequency.
Some parameters like the max sample rate allowed are computed by the Windows application.No setup procedure necessary when going from the DRIXO to the EXO oscillator at the same frequency.
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Ok, I followed the procedure, but as I have only one EXO and one Drixo, each with 5.x crystal to compare the clocks first…I let the 24.x crystek in its place…The PC software regonized both clocks and saved the data.
But when I plug the Usb-Cable out or when repowering the Fifo/Dac I get a OSC Err message and the fifo wont work.
When I pull as well the 24.x crystek clock (so no 48/96/192 recordings playable anymore) and let only the 5.x Drixo as a clock, the PC software realizes this, saves this and the Fifo works.
I guess this used case 5.x external clock in combination with a local 24.x crystek 957 was not tested when the software/firmware was programmed…you made the assumption that its a either completely external clocks or completely local clocks i guess…can you fix this in the firmware or PC-software, so that this combination becomes possible ?
I want to take my time to compare EXO vs Drixo and their PSU options…but want to listen to all of my recordings, so a complete frequency missing hurts…
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The Well Audio
Unfortunately mixed frequencies are not supported.
While is supported single oscillator.When both oscillators are installed they must be different sample rate frequencies (1 x x44.1 + 1 x x48) and same fs multiple (5.6448MHz + 6.144MHz, 11.2896MHz + 12.288MHz and so on).
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Thats a pity…I have still as well a pair of pulsar clocks which are 45.x and 49.x…would this be possible to include in future firmware updates ?
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The Well Audio
Thats a pity…I have still as well a pair of pulsar clocks which are 45.x and 49.x…would this be possible to include in future firmware updates ?
Unfortunately it’s not possible because 45/49 MHz are not supported, max allowed oscillator frequencies are 22/24 MHz.
The only way to install 45/49 MHz oscillators is dividing them by 2.
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I tried to connect the sdtrans384 to the fifo…wave mode…no music…(yes, it shows it is playing the files with resolution etc)…are there different i2s dialects ?
sdtrans speaks I2S*2 LRCK (fs), MCLK (22.5792 or 24.576 MHz), DCLK (64 fs), SDAT +3.3V CMOS level output…?
I remember there was something about right-justified data or left-justified data (in theory)…but sofar have no experience with that, never came across that bridge before…if i got it right, sdtrans384 output Left justified…with the “LSB extension algorithm”…what ever this means…does the Fifo understand that dialect ? Any settings to be changed for that input ?
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The Well Audio
FIFO Lite accepts standard I2S only.
I2S is a standard interface: BCK, WS and DATA.
There are no settings.Please, ask the designer of the SdTrans how configure it to output standard I2S.
DAC Lite works only if driven by FIFO Lite, no other way since it use a custom protocol.
DAC Lite is a PCM DAC so it cannot play DSD.
We are working on a DSD DAC, but it’s a different board. -
Thanks…the other option to connect Sdtrans is via HDMI I2S Ps-Audio Standard…i believe you have the compatible Receiver board with the TWSAFB-RX ? Is that Ps-Audio Standard like described here https://www.diyaudio.com/community/threads/microsd-memory-card-transport-project.142562/page-10#post-2214403 ?
I think Hqplayer can be used to as well to output PCM, but not sure if that is a great idea to modify PCM upfront…the initial purpose was the DSD DAC without a DAC concept (http://puredsd.ru/) so a DSD generator as you know…but maybe I use the trial and see what it does..
…as your dac ist 24bit192( with the 5/6clocks) that would be the target upsampling I guess…
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The Well Audio
Yes, our TWSAFB-RX is compliant with HDMI I2S Ps-Audio.
DAC Lite plays up to 176/192 kHz with 5/6 MHz oscillators. And up to 384 kHz with 11/12 MHz oscillators.
FIFO Lite does not perform any upsampling, so any upsample should be performed externally before driving the FIFO Lite.
FIFO Lite accepts up to 384 kHz.DAC Lite has to be driven by the FIFO Lite, otherwise it does not work.
It does not provide any oversampling, it’s a NOS DAC.
It does not accept DSD, nor direct neither when driven by the FIFO Lite.There will be a DSD DAC board within 3-4 month. It will accept DSD only.
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A DSD board ? Is this than the sonic empire DAC ?
I tried Hqplayer briefly today…not yet my taste…less natural…less air/vibrations…(PCM output) used in 24/192 to serve the DAC…
The sdtrans plays now…was a stupid misunderstanding of handling it…is was showing the songs, but did not starting to play until you explicitly pressed play addionally…it plays now very nice, very natural, maybe sofar the best source (from a battery supply)…but from a sdcard…I need somthing like this playing from a NAS at least…connected to the clocks of the fifo (the sdtrans could in theory accept expertnat clock signals 22/24, but still SD and no nice Controll App like with MPD)…
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The Well Audio
No, the DSD DAC board is not the Sonic Empire DAC.
It’s an alternative to the DAC Lite we would like to try.
After the comparison between the DAC Lite and the DSD DAC we will choice the ultimate way for the Sonic Empire DAC.Glad that the SdTrans now works.
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jmmbarco
Yes, our TWSAFB-RX is compliant with HDMI I2S Ps-Audio.
DAC Lite plays up to 176/192 kHz with 5/6 MHz oscillators. And up to 384 kHz with 11/12 MHz oscillators.
FIFO Lite does not perform any upsampling, so any upsample should be performed externally before driving the FIFO Lite.
FIFO Lite accepts up to 384 kHz.DAC Lite has to be driven by the FIFO Lite, otherwise it does not work.
It does not provide any oversampling, it’s a NOS DAC.
It does not accept DSD, nor direct neither when driven by the FIFO Lite.There will be a DSD DAC board within 3-4 month. It will accept DSD only.
Hi Andrea. Could you please share some details about the DSD dac?
Will be using same 5/6(11/12) MHz oscillators? will it be driven by FIFO? and max sample rate?
best
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The Well Audio
The TWSDAC-DSD will work with both 5/6 MHz and 11/12 MHz oscillators.
With 5/6 MHz oscillators it plays DSD128 and with 11/12 MHz oscillators it plays DSD256.
It will be driven by the FIFO Lite, we will provide the FPGA firmware update.
It laso can driven by other source which provides balanced output since the DAC has balanced input.
Anyway we cannot guarantee the same performance we will reach with the FIFO Lite, because the FIFO Lite drives directly the DAC with master clock, so directly from the oscillators. DATA are optically isolated from the master clock. -
Ivan
Hi Andrea,
Can’t find info about TWSAFB-OI powering. Will it be OK to power it from FIFO’s (TWSAFB-LT) J27 3V3 output?
Thnaks.
Ivan.
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And the second question.
Seems like on your FIFO (TWSAFB-LT) there is no external xtal (clock) selection pin like it is realized on your separate TWTMC-STS-FSDO-S board. Is this means that I am forced to use another (separate) xtals/clocks for the I2S source as your FIFO is waiting for already formed I2S for proper clock freq recognition?
Some explanation of my existing working scheme. In my existing DAC I do use your DRIXO clocks for generating/creating of the I2S from the very beginning. It works this way:
BeagleBone Black (LAN-I2S endpoint, botic driver) sends the signal of 0 (44k) or 1 (48k) from the dedicated GPIO pins in accordance with the playing sampling rate (through my board with the isolator chip) to J7 header of your TWTMC-STS-FSDO-S. Your TWTMC-STS-FSDO-S switches between two clocks (45/49MHz) and sends the needed masterclock (through my board over the isolator chip) back to BBB. BBB creates the I2S from the incoming (correctly chosed) DRIXO masterclock and sends it to FIFO (and then to DAC).
What is my point? I do not like situation when the initial I2S is formed from the other xtals/clocks that are worse than your DRIXO clocks. Will be sad to lost a possibility of a single clocking scheme for the whole chain from I2S initiation till the DAC tacting itself.
My questions are relates to the upcoming order and I just want to be ready for your stuff will come some months later. Andrea what can you suggest in conjuction with the above described?
Thank you!
Ivan. -
The Well Audio
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Got it. Thx.
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The Well Audio
And the second question.
Seems like on your FIFO (TWSAFB-LT) there is no external xtal (clock) selection pin like it is realized on your separate TWTMC-STS-FSDO-S board. Is this means that I am forced to use another (separate) xtals/clocks for the I2S source as your FIFO is waiting for already formed I2S for proper clock freq recognition?
Some explanation of my existing working scheme. In my existing DAC I do use your DRIXO clocks for generating/creating of the I2S from the very beginning. It works this way:
BeagleBone Black (LAN-I2S endpoint, botic driver) sends the signal of 0 (44k) or 1 (48k) from the dedicated GPIO pins in accordance with the playing sampling rate (through my board with the isolator chip) to J7 header of your TWTMC-STS-FSDO-S. Your TWTMC-STS-FSDO-S switches between two clocks (45/49MHz) and sends the needed masterclock (through my board over the isolator chip) back to BBB. BBB creates the I2S from the incoming (correctly chosed) DRIXO masterclock and sends it to FIFO (and then to DAC).
What is my point? I do not like situation when the initial I2S is formed from the other xtals/clocks that are worse than your DRIXO clocks. Will be sad to lost a possibility of a single clocking scheme for the whole chain from I2S initiation till the DAC tacting itself.
My questions are relates to the upcoming order and I just want to be ready for your stuff will come some months later. Andrea what can you suggest in conjuction with the above described?
Thank you!
Ivan.The FIFO Lite detects the I2S sample rate family and automatically selects the proper clock.
If you want to drive the source with the same master clock of the FIFO you can simply get the MCK output from one of the u.fl connectors labelled MCK (J12 or J21).
It comes from the external oscillators (DRIXO in your case), it’s already converted to square wave and it’s already selected by the I2S input sample rate family.-
This reply was modified 1 year, 9 months ago by
Moderator.
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I think you do not understood. In my case the I2S is simply not exist untill I feeding the MCK to the BBB mck-in. Correct me if I wrong please.
1) Your FIFO is waiting for an independant incoming I2S and only after its presence at I2S input the FIFO’ logic is analyzing this incoming I2S for freqs (by BCK or LRCK – I don’t know which line exactly) and compares it with two masterclocks of Xtals/DRIXOs. If the freqs of the incoming I2S are not in-sync with the first xtal, then FIFO’s logic is switching to second xtal.
But what will be in my case? I see two scenarios.
2) Your FIFO is waiting for incoming I2S and as a result do not generates MCK at all as BBB can’t make I2S without incoming MCK. Game over.
3) Your FIFO is generating MCK randomly. Xtal1 for example or last previously used – I don’t know which exactly, but for clarity reason let it be 11.2896MHz (44k1 family rate).
3a) I play music in 44k1 family rate, CDDA format. BBB generates the I2S at the “sonically correct speed”, your FIFO compares this incoming I2S with 11.2896MHz Xtal -> it is matching. Result: lucky case – everything is OK.
3b) I play music in 48k, DVDA (96k) format. BBB generates the I2S at the “sonically incorrect speed”, but your FIFO compares this incoming I2S with 11.2896MHz Xtal and as a result do not recognizing that anything is wrong as the incoming I2S was created from this 11.2896MHz MCK. Result: Music plays at incorrect speed. Game over.
The 3rd scenario is not a theory, but it is based on my existing situation (with Ian’s fifopi). I have solved this using your TWTMC-STS-FSDO-S board for proper MCK freq selection as BBB has a dedicated pins which sends 0 or 1 to your TWTMC-STS-FSDO-S board before starting playback (before generating I2S).
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This reply was modified 1 year, 9 months ago by
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The Well Audio
When the FIFO Lite starts the x48 oscillator family is selected.
Moreover the FIFO Lite auto-performs oscillators selection when the I2S input signal is detected, and there is no way to manually select between the oscillators.So the only way could be using a pair of splitters after the oscillators (one for each oscillators) to send the MCK to both FIFO Lite and TWTMC-STS-FSDO-S boards.
This way the FIFO Lite is fed by the MCK and the proper oscillator is selected, and also the BBB will receive the MCK by the TWTMC-STS-FSDO-S. -
Moreover the FIFO Lite auto-performs oscillators selection when the I2S input signal is detected, and there is no way to manually select between the oscillators.
Sad story.
So the only way could be using a pair of splitters after the oscillators (one for each oscillators) to send the MCK to both FIFO Lite and TWTMC-STS-FSDO-S boards.
This way the FIFO Lite is fed by the MCK and the proper oscillator is selected, and also the BBB will receive the MCK by the TWTMC-STS-FSDO-S.Adding another large board (like TWTMC-STS-FSDO-S) in addition to your FIFO board looks a bit overkilling decision, definitely unwanted entity.
Nevertheless,
Andrea, the main question actually is:Does the followed 2 connections scenarios are really equal in terms of I2S quality after your FIFO(+DRIXOs) ?
1. Work with independantly formed I2S (made from a regular quality xtals/clocks like NDK’s NZ2520SDA or Accusillicon’s 318b)
vs
2. Work with I2S formed from the same DRIXO’s clocks as used for FIFO itself
Answering to this question will help me to understand what is really better: simply to add a pair of a regular xtals on top of BBB (there is a project from Pavel Pogodin called PPY`s ReClocker here: puredsd.ru) for prepare an independant I2S before your FIFO for proper DRIXOs selection;
or to follow the usage of an extra multiplexers and boards to make a solid syncing scheme from the I2S creating till its correction through your FIFO.
Thank you!
p.s. I think that second approach is more correct and really can’t understand why did you excluded the possibility of external (manual clock selection) as it was realized on a separate squarer FSDO board.
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The Well Audio
The FIFO Lite isolates the DAC from the source, since they work in separate time domains.
So we suggest the first approach, DRIXO oscillators feed the FIFO Lite only.
Finally, it’s a little complex to explain why the FIFO Lite does not accept external control of the clock selection. I should explain all the hardware and software architecture.
What I can say is that without the auto-selection of the master clock the FIFO Lite cannot work, unless we redesign all this architecture. -
What I can say is that without the auto-selection of the master clock the FIFO Lite cannot work, unless we redesign all this architecture.
Sure Andrea. I just want to understand how to proceed.
So we suggest the first approach, DRIXO oscillators feed the FIFO Lite only.
OK. This means that I do not need to buy extra FSDO boards.
Honestly… It is VERY HARD for me to believe that it is absolutely doesn’t matter how bad was the masterclock(s) during the I2S generatng/initiation before your FIFO(+DRIXOs). But OK, I think I will have enough DRIXO clocks to check there influence before FIFO. I will came back later with conclusions.
Thanks for answers!
Ivan.
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lasercut
I’m trying to connect the FIFO to TDA1387, it needs a standard i2s input. The FIFO doesnt seem to allow LRCK output to be used with i2s output, only WS output from the uC (which is the same signal as far as I know).
Any reason for this? -
The Well Audio
I2S output (input for the TDA1387) means continuous clock, so the clean side of the FIFO cannot be used.
You have to use the signals coming from the FPGA (BCK, DATA and WS) as showed by the Windows app.The only way to improve the jitter is using the OIR board which performs the reclock of both BCK and WS (LRCK).
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Shot in the dark but do you know if using 2 seperate TDA1387s could allow a workaround to use a stopped clock format, DR and DL signals to each or something like that?
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The Well Audio
Looks like the TDA1387 does not support simultaneous mode like the TDA1541A, so I believe there is no way.
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Ok, thanks for the help as always.
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minionas
Hi all,
Im wondering if anyone uses this fifo connected to rpi with Moode software. If yes, the what i2s device settings in Moode you use?
Thanks in advance for any input.
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I used the RPI with the FIfo, but not with Moode. The Dam1021 setting works normally.
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slmnklyc
Hi.Let’s say we play a music video from pc while using the fifo reclocker in the chain.
Will be any noticiable sound delay wrt to video?
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The Well Audio
I’m not an expert about music video reproduction so I could be wrong.
The minimum buffer size is 65kb, which corresponds to 23 ms delay playing 16 bit/44.1 kHz and 5.2 ms playing 24 bit/192 kHz.
Maybe there is a software option to set the video delay in order to compensate the music delay.
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I see optical isolator chips on the fifo reclocker outputs and dac inputs.
There is an idea that optical isolators are not so good for hifi audio.I don’t know the chips but I think there are digital/magnetic isolator chips..Like adum chips use on i2s level..
What do you think about this,and can we bypass them?
Can we use ad1862 dac board without the reclocker,it looks I can’t use?
And What happens ad1862 take 24bit audio input? Does it truncate it to 20bit inside the dac chip or truncate/dither on fifo reclocker board?
Thanks,the boards looks cool!
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The Well Audio
They are high speed optical isolators.
They don’t affect the audio signals since they carry the dirty parts of the audio digital signals (BCK and DATA).
The only crucial signal for PCM DACs like AD1862, TDA1541A and our DAC Lite is the LRCK, which comes directly from the clean section of the FIFO Lite (Master clock and dividers), and this clock comes via copper.
You cannot bypass them, and moreover it would be wrong because the optical isolators are just used to isolate the dirty and the clean part of the digital audio signal, so that the signals coming from the FPGA of the FIFO Lite cannot affect the DAC.You could use the AD1862 DAC board without the FIFO Lite but since the DAC has sign magnitude notation you have to drive it with such architecture (LRCK, BCK, DRP, DRN, DLP, DLN).
When ad1862 take 24bit audio input you can select one of the 8 dithering options, which include truncate.
If you download the Windows application you can see by yourself the available options and setting parameters in unplugged mode. -
nguyen phuong
Hi, when I connect signal via I2S from Asynchronous FIFO buffer to Transmitter I2S over HDMI, Which signal should I connect between two board ( MCLK, BCK, LRCK, DATA, ground ?).
Tks. alot for your help
Phuong
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The Well Audio
You cannot connect directly the I2S over HDMI transmitter to the FIFO Lite because the transmitter has LVDS output.
So you need the I2S over HDMI receiver TWSAFB-RX-F which converts LVSD to single ended to feed the FIFO Lite. -
Dear.
May be you mis-understood me
signal from ERED-DOCK board (via I2S) to — FIFO LITE —- then go out from FIFO LITE (via I2S) to HDMI Transmitter . From HDMI Transmitter, signal go out via I2S over HDMI to digital active crossover.
My digital active crossover could not receive I2S signal (over HDMI) from HDMI Transmitter, may be I connect I2S cable from FIFO LITE to HDMI TRANSMITTER WRONG.
please help me
Tks Phương
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The Well Audio
Does your digital crossover accept LVDS signals?
If not you should connect the output of the FIFO Lite directly to your digital crossover.
Anyway the output of the FIFO Lite depends on the DAC configuration you have selected, please let me know your FIFO settings.
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Hi
My digital active crossover got an I2S differential over HDMI port (with PS Audio standard. ES9038 PRO). This product from
Analog-precision.com (ultimate Preamplifier)
tks
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The Well Audio
Without the FIFO settings I cannot say where to take the output.
Which DAC you have selected when you have configured the FIFO Lite?
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HI
1. about FIFO setting: I connect pin I2S out on Ered Dock board to Port I2S1 in (on FIFO Lite) as follow
– Pin 1, 3, 5, 7, 11 on Ered Dock (Ground) to Ground pin on Port I2S1 in FIFO Lite BOARD
– Pin 2 on Ered Dock (MCK)– MCK pin on Port I2S1 in FIFO Lite BOARD
– Pin 6 on Ered Dock (BCLK) — BCK pin on Port I2S1 in FIFO Lite BOARD
– Pin 8 on Ered Dock (PCM-LRCLK) — LRCLK pin on Port I2S1 in FIFO Lite BOARD
– Pin 12 on Ered Dock (PCM_SDATA/DSL) — DATA pin on Port I2S1 in FIFO Lite BOARD
(I send the table on pdf file insert, so that you can easily imagine)
2.DAC that I chosen when I have configured the FIFO Lite ?. because the I2S out from board Transmitter I2S over HDMI then go in to another I2S on HDMI is diffenretial I2S, so may be we need not chose DAC ??
Am I right or not ? I”m not good in electronic, sorry.
Tks
Phương
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The Well Audio
Connections between Ered Dock and FIFO Lite look correct.
Then you need to configure the FIFO Lite using the Windows app
https://www.thewellaudio.com/wp-content/uploads/App/TWSAFBLTSet/TWSAFBLTSet.applicationPlease download the user manual of the FIFO buffer (TWSAFB-LT) and follow the instructions
https://www.thewellaudio.com/wp-content/uploads/TWSAFB-LT_User_Manual.pdfI think the settings you have to use are as in the attached picture
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Hi.
when connect I2S out from FIFO lite (dupont standard) to HDMI I2S board (dupoint. this board don’t have UFL standard in for I2S). which signal leg should I connect (BCK, DATA, MCK, LRCLK ?). tks – Phương
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I2S dupoint out from FIFO lite should use J8 or J26 and which signal should I connect to HDMI I2S board ? ( I sent 2 attachment). tks Phuong
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The Well Audio
After you have configured the FIFO Lite by the Windows app as in the attached picture you have to connect:
– FIFO J8 BCK to TX J2 BCK
– FIFO J8 DRDT to TX J2 DATA
– FIFO J8 DLWS to TX J2 LRCK
– optional FIFO J8 MCK to TX J2 MCK -
Hi, there may be somethings wrong when I connect ERED-DOCK I2S out to I2S in port 1 on FIFO.
So, I need your help.
Which signal from I2S out (off Ered Dock) to I2S in Port 1 (in FIFO lite)
https://www.engineered.ch/products/ered-dock/
1= GND = Ground for I/O and clock management.
2 = MCLK = Master Clock Output – Master clock output at 22.5792MHz or 24.576MHz.
3 = GND = Ground for I/O and clock management.
4 = SPDIF = S/PDIF Output – Serial encoded PCM audio data stream, TTL level.
5 = GND = Ground for I/O and clock management.
6 = BCLK = Serial Audio Bit Clock Output – Serial bit clock for PCM and DSD audio data.
7 = GND = Ground for I/O and clock management.
8 = PCM_LRCLK =Serial Audio Left/Right Clock Output – Frame sync clock for PCM audio data.
9 = GND = Ground for I/O and clock management.
10 = PCM_SDATA1 = /DSDR = Serial Audio Data DSD right-channelOutput audio data.
11 = GND = Ground for I/O and clock management.
12 = PCM_SDATA0 = /DSDL Serial Audio Data Output Stereo PCM audio data / DSD left-channel audio data.
13 = GND = Ground for I/O and clock management.
14 = MUTE # Mute signal
Low: the audio data stream is not valid and the DAC must be muted.
High: the audio data stream is valid.
15 = DSD_PCM# = Audio Stream Format
Low: the digital audio output stream format is PCM.
High: the digital audio output stream format is DSD.
16 = 44K1_EN# Sampling Frequency
Low: the sampling frequency is a multiple of 44.1kHz.
High: the sampling frequency is a multiple of 48kHz. Refer to Table 4-1.
17 = RATE0 = Sampling Rate – Sampling rate information. Refer to Table 4-1.
18 = RATE1 = Sampling Rate – Sampling rate information. Refer to Table 4-1.
19 = reserved = Unused. Do not connect.
20 = GND = Ground for I/O and clock managementThe attachment is the Í2S signal out from ered dock
Please help me: Which signal from I2S out (off Ered Dock) to I2S in Port 1 (in FIFO lite)
Tks
Phương
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The Well Audio
I don’t know how Ered Dock outputs I2S.
I could assume:
– Ered-Dock pin 12 PCM_SDATA0/DSDL to FIFO Lite J14 pin 1 DATA
– Ered-Dock pin 13 Ground to FIFO Lite J14 pin 2 GND
– Ered-Dock pin 6 BCLK to FIFO Lite J14 pin 3 BCK
– Ered-Dock pin 7 Ground to FIFO Lite J14 pin 4 GND
– Ered-Dock pin 8 PCM_LRCLK to FIFO Lite J14 pin 5 LRCK
– Ered-Dock pin 9 Ground to FIFO Lite J14 pin 6 GND
– optional Ered-Dock pin 2 MCLK to FIFO Lite J14 pin 7 MCK
– Ered-Dock pin 3 Ground to FIFO Lite J14 pin 8 GNDI’m not sure because they listed SDATA0 and SDATA1 while I2S has DATA only (both channel alternating). I assume DATA0 because they specified “Stereo PCM audio data”.
Please, ask the manufacturer to confirm.
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tks so much
Phương
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Hi theWell audio
I got 2 problem with FIFO lite that I need your help
1. FIFO LITE cannot detect the OSCILATOR 5.6448 MHz : I got two OSCILATOR (TWTMC-DRIXO –F 5.6448 MHz with 6.448M Hz SC-cut and TWTMC-DRIXO –F 6.1440 MHz with 6.1440MHz SC-cut). In the third time of turning on the system (until now): the FIFO lite not detect clock 5.6448. (It can dectect clock 5.6448 just in the first and the second time only), FIFO lite fail or TWTMC-DRIXO –F 5.6448 MHz fail ?. what should I do now
2. FIFO lite can not send I2S out in the right way to TWSAB-LT : I have been setup / config FIFO lite as your instruction. And I connect cable for I2S as your instrucion. My digital active crossover with I2S in (PS audio standard) can not receive I2S signal. May be I should ask you a gain about software setup. (1) Do we have to chose DAC ? (I used TWSAFB-LT to send I2S diferential via HDMI cable) (2) in advanced setup: which option should I chose).
Tks, Phuong
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The Well Audio
1) We test all the boards, so both oscillator worked before shipping.
When the FIFO does not recognize the master clock it depends on the oscillator.
Please, try switching of and on the oscillator, and after a minute or so light on the FIFO.2) The FIFO settings look correct. Have you saved them in the EEPROM as for User manua instructions?
If so the I2S output should be correct on the pisn I have previous listed.
TWSAFB-TX HDMI connection in the attached picture, the same of PS Audio standard (attached).Have you an oscilloscope?
Without an oscilloscope the remote debugging is difficult. -
emyeuoi
Hi Phuong,
i am an happy owner of the Andrea FIFO, clocks and DAC Lite.
i live in Vung Tau, Vietnam. From you posts I understand that you are in trouble with the FIFO.
if you live in Vietnam and I can help you let me know.
Dear Andrea,
i know that I promise to post some pucs and impression of your amazing DAC… too much to do at work in this period 🙂
I want to attach here few pics but the size allowed is 512K and i can’t.
Tomorrow I will try to resize but I can promise that I will succed
How it sound? I have to say that the first impression was not really good, there was a kind of lack of low frequencies and the high was too prominent. As you suggest I let burn-in and now, after almost one month, the DAC play really well, amazing 3D, absolutely silent with no signal, everything is there in the right position… amazing job you did Andrea! Thanks!
Cheers,
Enrico
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<p style=”text-align: left;”>Hi Entici, nice to meet you again. I still keep your phone number . . .4486.</p>
I will contact you.Tks so much
Phương
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1) We test all the boards, so both oscillator worked before shipping.
When the FIFO does not recognize the master clock it depends on the oscillator.
Please, try switching of and on the oscillator, and after a minute or so light on the FIFO.2) The FIFO settings look correct. Have you saved them in the EEPROM as for User manua instructions?
If so the I2S output should be correct on the pisn I have previous listed.
TWSAFB-TX HDMI connection in the attached picture, the same of PS Audio standard (attached).Have you an oscilloscope?
Without an oscilloscope the remote debugging is difficult.Hi
1. about not reconize x44.1 clock: the problem is long USB cable (3m), when I used 1m USB cable, the application reconnect boths clock very fast (with 3m USB cable, the application take a very long time to connect to FIFO lite , and it cannot reconize the 44.1 Hz clock. DONE, so happy
2. TWSAFB-TX HDMI board work quite well: when I connect this board to RBI or ERED-DOCK, TWSAFB-TX HDMI board send I2S signal via HDMI success, (Dac mute light on my digital active crossover turn Off and and my system give sound out). But when TWSAFB-TX HDMI board connect to FIFO lite, TWSAFB-TX HDMI board not success in sending I2S out in the right format ( Dac mute light on my digital active crossover still turn on and and my system give no sound). I’ve already checked the connection pin lots of time (yes it’s connected in the way you show me). so, the problem is Format I2S signal out in the right way (excuseme, but, are you sure that the connection pin you show me is RIGHT ?).
Tks, Phuong
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The Well Audio
Yes, the connections and the FIFO Lite settings are the ones in post #2086.
FIFO Lite outputs standard I2S with such that settings (32 + 32 bits of DATA, 3.072MHz/6.144MHz or 2.822MHz/5.6448MHz BCK depending on the input sample rate 48/96kHz or 44.1/88.2kHz, 48/96kHz or 44.1/88.2kHz WS depending on the input sample rate).
Does your digital crossover accept standard I2S?
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<p style=”text-align: left;”>Yes. my digital active crossover accept I2S over HDMI port. I use it with 3 component with I2S out ( Pi2 design, and 2 I2S over HDMI out from I An (Canada) that I forget name..It’s work quite well.</p>
Tks anyway. I will try to find what ‘ s the problemPhương
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Hi
When I Up Fir.ware from 240 to the new firmware (maybe 390) I nolonger chose SELECT A DAC. When I select a DAC. I will see this warning message ( pic insert). I want to select DAC, How can I do
Tks
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Hi
When I Up Fir.ware from 240 to the new firmware (maybe 390) I nolonger chose SELECT A DAC. When I select a DAC. I will see this warning message ( pic insert). I want to select DAC, How can I do
Tks
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The Well Audio
Maybe something has gone wrong during the installation.
Please follow the following steps:
– Uninstall the Windows application TWSAFB-LT Settings
– Install the Windows application TWSAFB-LT Settings from https://www.thewellaudio.com/wp-content/uploads/App/TWSAFBLTSet/TWSAFBLTSet.application
– Open the Windows app, connect the TWSAFB-LT by USB cable and then upgrade the firmware from https://www.thewellaudio.com/wp-content/uploads/TWSAFB-LT_FPGA_firmware.zip -
Hi.
I Tried in that way but no help. It’s seem missing some files ?
tls
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this happened after I Up Firmware and RESET MCU.
Is this the cause ?
tks
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Hi Andre
Now My system can sing, So happy. I have 2 question
1. With TWTMC-DRIXO Driscoll oscillator and clock 5,6 MHz , 6.2 MHz: I can play file 44,1 – 88,2 – 96, but not 192 Khz ? How can I do to play 196 KHz (change setting ? buy some more component ?
2. As in threat post 2125: When I run TWSAFB-LT from laptop I cannot select DAC, but when I run from a nother PC (DESKTOP), I can still select DAC, this happen maybe after I reset MCU and up firmware from 240 tp 303. May be the laptop missing some file (I’ checked and Microsoft.net still there), do I need some more software
Tks
Phuong
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The Well Audio
1. the simplest way is you get a pair of TWTMC-DBM frequency doublers: 5 to 11 MHzx and 6 to 12 MHz
2. looks like your installation on the laptop is corrupted since the assembly System.Data.SQLite.dll is missing. Please navigate C:\Users\yourusername\AppData\Local\Apps\2.0….\ and check inthe installation folder, you should find the objects as in the attached picture. If anything is missing the application is corrupted, and so yo need to unistall and reinstall the application. Uninstall the application from Control Panel/App and then delete all the isntallation folders you find (it could be multiple versions). Finally reinstall the application following the steps listed in the previous post.
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Sebastian
Hello Andrea, is a 7.5V Meanwell medical grade wall mount power supply ok for the fpga side of the fifo, both because of the voltage and quality wise?
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The Well Audio
If it’s a switching power supply I wouldn’t use it.
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Hi Andrew
with 5.6448 MHz SC-Cut + TWTMC-DRIXO-F-5.6448 MHz
and 6.1440 MHz SC-Cut + TWTMC-DRIXO-F-6.1440 MHz
supported Max SR: 88.2/96 Khz,
In case I want to support 176,4/192 khz, I will use doubler
1. TWTMC-DBM-F 5.6448 MHz to 11.2896 MHz (New Frequency doubler 5.6448 MHz to 11.2896 MHz)
2. TWTMC-DBM-F 6.144 MHz to 12.288 MHz (New Frequency doubler 6.144 MHz to 12.288 MHz)
Is this compatible ? and is this the best for sound ?
Do we need to buy any more ? (do I need to buy Frequency doubler transformers kit: TWTMC-DBM-XFMR ?)
and are they avalable
Tks
Phuong
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The Well Audio
Yes, it’s compatible and it’s the best option to get the lowest phase noise at 11.2896 MHz and 12.288 MHz.
You don’t need the transformers kit, they are already installed on the finished board.
Unfortunately no boards available now, but hopefully we will start a new GB in a few weeks, since several new designs are available included the new DSD discrete DAC. -
<p style=”text-align: left;”>Hi Andrew. do I need to send money for back order. or I send email, when having board you tell me to pay</p>
tks. Phương -
The Well Audio
Please, let me start the new GB and after you can send the order form.
You will pay before shipping. -
Hi Andrew
because of the best for sound, I want to supply power 7 volt for FIFO LITE with batterty (LiFe, Lithium Titanate, . . . ), so I wish to know more about MIN VOLT and MAX VOLT for 7 volt input on FIFO LITE,
tks
Phuong
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The Well Audio
You should stay between 6V5 and 7V5.
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Hi Andrew
I think My Driscol oscilator fail
On the reply 2110, I happy to say that, My system work.
But it work for just 2 day, on the third Day, after I on and off the power of the system (include clock). the Clock stop working again , My FIFO LITE can not detect 44.1 Mhz. I try lots of time, but, can not detect.
I borrow another clock (Driscol 22 and 24 Mhz from emyeuoi (Enrico, his on this post also) , my system detect very fast, and it sing again
may be the problem: “” .6448 MHz and 6.144 MHz crystals have very high Q (more than 2M) and high ESR. With some
crystals the oscillator needs long time to start and sometimes it doesn’t even start. In this case you
can replace R24 (1K) with 1.2K, 1.5K or 1.8K resistor so it will start faster.””any Idea ?
Tks
Phuong
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The Well Audio
Without an oscilloscope it’s difficult to say.
All the finished boards have been tested before shipping.
The DRIXO at 5/6 MHz could take several seconds to start since the Q of the crystals are very high.You could try replacing R24 as I suggested up to 2-2.2k to see if it starts faster.
You could also try powering on the oscillators 1 minute or so before powering the FIFO.
Anyway to get the best performance from the oscillators they shouldn’t never power off.
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I am experimenting with supercapitors as PSU which are very nice…by coincidence I found that the drixo starts to work nicely from 8V up…can you confirm the minimum voltage ? The manual originally stated 12V…but the lower the possible voltage, the longer the charge of a supercap would last before recharging…
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The Well Audio
Sorry, never tried below 12V.
Moreover we have never measured the phase noise below 12V. -
skilion7
Hi, there may be somethings wrong when I connect ERED-DOCK I2S out to I2S in port 1 on FIFO.
So, I need your help.
Which signal from I2S out (off Ered Dock) to I2S in Port 1 (in FIFO lite)
https://www.engineered.ch/products/ered-dock/
1= GND = Ground for I/O and clock management.
2 = MCLK = Master Clock Output – Master clock output at 22.5792MHz or 24.576MHz.
3 = GND = Ground for I/O and clock management.
4 = SPDIF = S/PDIF Output – Serial encoded PCM audio data stream, TTL level.
5 = GND = Ground for I/O and clock management.
6 = BCLK = Serial Audio Bit Clock Output – Serial bit clock for PCM and DSD audio data.
7 = GND = Ground for I/O and clock management.
8 = PCM_LRCLK =Serial Audio Left/Right Clock Output – Frame sync clock for PCM audio data.
9 = GND = Ground for I/O and clock management.
10 = PCM_SDATA1 = /DSDR = Serial Audio Data DSD right-channelOutput audio data.
11 = GND = Ground for I/O and clock management.
12 = PCM_SDATA0 = /DSDL Serial Audio Data Output Stereo PCM audio data / DSD left-channel audio data.
13 = GND = Ground for I/O and clock management.
14 = MUTE # Mute signal
Low: the audio data stream is not valid and the DAC must be muted.
High: the audio data stream is valid.
15 = DSD_PCM# = Audio Stream Format
Low: the digital audio output stream format is PCM.
High: the digital audio output stream format is DSD.
16 = 44K1_EN# Sampling Frequency
Low: the sampling frequency is a multiple of 44.1kHz.
High: the sampling frequency is a multiple of 48kHz. Refer to Table 4-1.
17 = RATE0 = Sampling Rate – Sampling rate information. Refer to Table 4-1.
18 = RATE1 = Sampling Rate – Sampling rate information. Refer to Table 4-1.
19 = reserved = Unused. Do not connect.
20 = GND = Ground for I/O and clock managementThe attachment is the Í2S signal out from ered dock
Please help me: Which signal from I2S out (off Ered Dock) to I2S in Port 1 (in FIFO lite)
Tks
Phương
I’m using eREDock.
using it by connecting to a dac that receives i2s input.The data output pin was 12.
eREDock firmware v1.58 is currently experiencing many problems.
connection gets cut off often
It often disappears from the networkDo not update the eREDock firmware
If you have an old version of eREDock firmware, can you send it to me?
1.37 , 1.39 , 1.41
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The Well Audio
I don’t own eREDock board, so I’m sorry I haven’t any firmware.
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Kazuma
I have these firmwares of eRed-mod:
but 512kb maximum size allowed, cannot attach here
Andrea, can you bump the limit to 10mb?
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iansr
Is this FIFO buffer compatible with the DDDAC (PCM 1794)? Are you aware of anyone who has done this?
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The Well Audio
Our FIFO can drive the DDDAC1794 with and without mother board.
You can see some pictures and comparisons here
https://www.diyaudio.com/community/threads/the-battle-of-the-dacs-comparison-of-sound-quality-between-some-dacs.386815/ -
Hi Andrew.
I have bought frequency doubler frm you, power supply: 12-24 volt, but what is the best voltage to them (about sound quality): from ? to ?
Tks
Phuong
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hollowman
Hi All:
I was long-time Hollowman (and many aliases) on DIYA. Banned, there, of course for challenging the groupthink 😉
Kudos to andrea mori for creating this thewellaudio.com site/forum as an alternative to DIYA!
My main question is how the andrea mori FIFO project differs from the IANCANADA fifo project. I can’t find Ian’s schematics nor can I (of course) post on DIYA to enquire about specifics.
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The Well Audio
Hi All:
I was long-time Hollowman (and many aliases) on DIYA. Banned, there, of course for challenging the groupthink 😉
Kudos to andrea mori for creating this thewellaudio.com site/forum as an alternative to DIYA!
My main question is how the andrea mori FIFO project differs from the IANCANADA fifo project. I can’t find Ian’s schematics nor can I (of course) post on DIYA to enquire about specifics.
Follows some features you can get from our FIFO buffer but you cannot find in Iananada’s FIFO (in brackets):
Inputs: 4 x selectable I2S input (1 input)
Output format: compatible with almost all modern and old DACs (I2S/DSD DACs only, for PCM you need the I2S to PCM board)
Custom output format: for TDA1541A (offset binary), TWSDAC-LT DAC Lite, Soekris DAM1021 upgrade, AD5791, TDA1541A and AD1862 dual mono sign magnitude (not available)
Dither: 8 x selectable dither depth separately for each source (not available)
FIFO buffer depth: 8 x selectable buffer depth separately for each source, from 65kb to 8Mb (not available)
Optional: digital DAC calibration to reach the best precision, TWSDAC-LT DAC Lite and maybe other DACs (not available in DSD mode); Return to Zero logic for DSD output format (not available)
Configuration: all settings can be configured one time by USB connection to the Windows application (not available)
Master Clock selection: T-switch configuration relais to select the sample rate family instead of multiplexers (multiplexers)
Optical isolation: MCK and LRCK optical isolated from the FPGA and the micro to avoid interferences (RF isolation)
External Master Clock: SMA connectors for external clocks with sine to square converter on board (you have to add SinePI to convert from sine to square)
Direct clock output: LRCK directly from the MCK (optical isolation) instead of from the FPGA (not avalable)
Phase noise: very low phase noise outputs (higher phase noise as measured)
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Is there a way to switch the display of the optional User Input board off ? I use it seldomly and it shines a bit bright for my taste…
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The Well Audio
The only way is detaching the flat cable.
If you want to lower the brightness you should replace 35 resistors (all the resistors on the UI board) with higher value, such 270R or 330R.
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Or stick a piece of car-window-tint-film on top of display to mute light
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seafood2017
Hi Andrew.
Have you measure the phase noise of LRCK? How many dBs is it better than MCK?
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The Well Audio
More than 40dB at 0.1Hz from the carrier.
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Hi , I’m not a expert, if I am wrong please correct me.Why is there no 40dB improvement above 10Hz?I have read a paper that mentions the white noise of traditional digital frequency dividers is affected by aliasing. Is this the reason?untitled (rubiola.org)
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The Well Audio
Already tried and measured.
It works fine to get sine wave output, but with CMOS output the resulting phase noise is the same of digital dividers.
So it does not worth. -
Thank you for sharing. You’re doing a great job.
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Hi Andrea. As I have already told you, I am using FIFO Lite to mod my TDA1541A tube DAC. DAC works in standard I2S mode.
For simplicity, as there are so many boards and regulators I have to install in my current chassis, I had decided not to add the OI board in the setup.Do you think I should reconsider this? I mean, as LRCK is already clean and reclocked from DRIXO, how important is to isolate bck and data?
In case I finally install, should the TWRPS-LT regulator 4V (50mA) be enough for powering FIFO clean side (30mA) and OI board (20mA)?
Best regards
Jm-
This reply was modified 7 months, 1 week ago by
jmmbarco.
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This reply was modified 7 months, 1 week ago by
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The Well Audio
It depends on the operating mode of the TDA1541A.
If you are planning to drive your DAC by the FIFO buffer in standard I2S mode then the TWSAFB-OIR is strongly recommended since the clock signals (BCK, LRCK) coming from the FIFO are dirty signals, they come from the dirty side of the FIFO.
Indeed in the Windows app used to configure the FIFO buffer you can find the option named “Generic TDA1541A I2S OIR option”.
This way the dirty clock signals are reclocked by the MCK, so the jitter coming from the dirty side of the FIFO buffer is eliminated.BTW, the best operating mode for the TDA1541A is the so called “Simultaneous mode” (BCK, DR and DL from the dirty side and LRCK from the clean side of the FIFO). In this case the TWSAFB-OI is the right otpion since it provides optical isolated BCK, DR and DL (and clean LRCK).
The 4V output from the TWRPS-LT is enough to power also the TWSAFB-OIR or the TWSAFB-OI. -
Thanks Andrea. Now understood.
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Hi.I see a new usb input version of the board.Will there be aes3/spdif input version of the fifo lite board?
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The Well Audio
Yes, we will provide SPDIF input interface but we cannot estimate the time to get the board available.
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