The Well synchronized asynchronous FIFO buffer – Slaved I2S reclocker

Forum Digital line The Well synchronized asynchronous FIFO buffer – Slaved I2S reclocker

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    • #1592
      The Well Audio
      Participant

      This topic is about FIFO buffer and re-clocker to be used between digital sources and DACs in order to mitigate the incoming jitter.

      You can find the original thread on diyaudio.com at the following link

      https://www.diyaudio.com/community/threads/the-well-synchronized-asynchronous-fifo-buffer-slaved-i2s-reclocker.348074/

    • #1612
      Olivier
      Participant

      This forum is welcome, I wish it long life,

      I reduced the value of the Fifo Lite buffer,After some time with a value of 2M I went to 130 kb,I had better results with 130kB,improvement of space between instruments.

       

    • #1649
      multiblitz
      Participant

      Interesting…I am not yet there to change parameters, but clocks at the moment…

       

      So, currently it euns with Crystek 957 in sockets on board. My question (I guess to Andrea): What is the absolute minimum procedure needed to change now to the drixo or Exo (when I want to compare sound) ?

      I would guesstimate:

      – Powering off the fifo/dac and the drixo

      – Pull the crystek for 22.x out (while the 24.x stays at the moment)

      – Wire the Drixo to the Fifo

      – connect the usb cable to the fifo and connect it to the pc with the setup software

      – power on clock and fifo

      – setup the dac with the new 5.x frequency with the software and save

      – power off-on the fifo

       

      Correct ?

      Or does the Fifo finds the new frequency (going from 22.x to 5.x) automatically, so no PC-setup procedure needed ?

      or whould the crystek clock even automatically be ignored when attaching the drixo cable ?

       

      I do have the EXO as well ready to compare with Drixo (both on 5.x)…This I guess would be just wiring the other clock, but no changes in the Fifo software/ no setup procedure when going from drixo 5.x to exo 5.x, right ?

       

       

    • #1655
      The Well Audio
      Participant

      Correct, the FIFO does not recognize the different oscillator frequency.
      Some parameters like the max sample rate allowed are computed by the Windows application.

      No setup procedure necessary when going from the DRIXO to the EXO oscillator at the same frequency.

    • #1660
      multiblitz
      Participant

      Ok, I followed the procedure, but as I have only one EXO and one Drixo, each with 5.x crystal to compare the clocks first…I let the 24.x crystek in its place…The PC software regonized both clocks and saved the data.

       

      But when I plug the Usb-Cable out or when repowering the Fifo/Dac I get a OSC Err message and the fifo wont work.

       

      When I pull as well the 24.x crystek clock (so no 48/96/192 recordings playable anymore) and let only the 5.x Drixo as a clock, the PC software realizes this, saves this and the Fifo works.

      I guess this used case 5.x external clock in combination with a local 24.x crystek 957 was not tested when the software/firmware was programmed…you made the assumption that its a either completely external clocks or completely local clocks i guess…can you fix this in the firmware or PC-software, so that this combination becomes possible ?

      I want to take my time to compare EXO vs Drixo and their PSU options…but want to listen to all of my recordings, so a complete frequency missing hurts…

       

    • #1662
      The Well Audio
      Participant

      Unfortunately mixed frequencies are not supported.
      While is supported single oscillator.

      When both oscillators are installed they must be different sample rate frequencies (1 x x44.1 + 1 x x48) and same fs multiple (5.6448MHz + 6.144MHz, 11.2896MHz + 12.288MHz and so on).

    • #1663
      multiblitz
      Participant

      Thats a pity…I have still as well a pair of pulsar clocks which are 45.x and 49.x…would this be possible to include in future firmware updates ?

    • #1665
      The Well Audio
      Participant

      Thats a pity…I have still as well a pair of pulsar clocks which are 45.x and 49.x…would this be possible to include in future firmware updates ?

      Unfortunately it’s not possible because 45/49 MHz are not supported, max allowed oscillator frequencies are 22/24 MHz.

      The only way to install 45/49 MHz oscillators is dividing them by 2.

    • #1759
      multiblitz
      Participant

      I tried to connect the sdtrans384 to the fifo…wave mode…no music…(yes, it shows it is playing the files with resolution etc)…are there different i2s dialects ?

       

      sdtrans speaks I2S*2 LRCK (fs), MCLK (22.5792 or 24.576 MHz), DCLK (64 fs), SDAT +3.3V CMOS level output…?

       

      I remember there was something about right-justified data or left-justified data (in theory)…but sofar have no experience with that, never came across that bridge before…if i got it right, sdtrans384 output Left justified…with the “LSB extension algorithm”…what ever this means…does the Fifo understand that dialect ? Any settings to be changed for that input ?

    • #1760
      Kazuma
      Participant
      Blitz Said

      Is anyone using HQplayer btw in combination with this FIfo/DAC (I guess with DOP of i2soverusb) ?

      There is no way for DAC to playback DSD streams, that are HQplayer software’s point.

      DAC designed for PCM. I heard Andrea’s planning to design a separate DSD DAC though.

    • #1763
      The Well Audio
      Participant

      FIFO Lite accepts standard I2S only.

      I2S is a standard interface: BCK, WS and DATA.
      There are no settings.

      Please, ask the designer of the SdTrans how configure it to output standard I2S.

      DAC Lite works only if driven by FIFO Lite, no other way since it use a custom protocol.

      DAC Lite is a PCM DAC so it cannot play DSD.
      We are working on a DSD DAC, but it’s a different board.

    • #1765
      multiblitz
      Participant

      Thanks…the other option to connect Sdtrans is via HDMI I2S Ps-Audio Standard…i believe you have the compatible Receiver board with the TWSAFB-RX ? Is that Ps-Audio Standard like described here https://www.diyaudio.com/community/threads/microsd-memory-card-transport-project.142562/page-10#post-2214403 ?

      I think Hqplayer can be used to as well to output PCM, but not sure if that is a great idea to modify PCM upfront…the initial purpose was the DSD DAC without a DAC concept (http://puredsd.ru/) so a DSD generator as you know…but maybe I use the trial and see what it does..

      …as your dac ist 24bit192( with the 5/6clocks) that would be the target upsampling I guess…

    • #1767
      The Well Audio
      Participant

      Yes, our TWSAFB-RX is compliant with HDMI I2S Ps-Audio.

      DAC Lite plays up to 176/192 kHz with 5/6 MHz oscillators. And up to 384 kHz with 11/12 MHz oscillators.

      FIFO Lite does not perform any upsampling, so any upsample should be performed externally before driving the FIFO Lite.
      FIFO Lite accepts up to 384 kHz.

      DAC Lite has to be driven by the FIFO Lite, otherwise it does not work.
      It does not provide any oversampling, it’s a NOS DAC.
      It does not accept DSD, nor direct neither when driven by the FIFO Lite.

      There will be a DSD DAC board within 3-4 month. It will accept DSD only.

    • #1769
      multiblitz
      Participant

      A DSD board ? Is this than the sonic empire DAC ?

      I tried Hqplayer briefly today…not yet my taste…less natural…less air/vibrations…(PCM output) used in 24/192 to serve the DAC…

      The sdtrans plays now…was a stupid misunderstanding of handling it…is was showing the songs, but did not starting to play until you explicitly pressed play addionally…it plays now very nice, very natural, maybe sofar the best source (from a battery supply)…but from a sdcard…I need somthing like this playing from a NAS at least…connected to the clocks of the fifo (the sdtrans could in theory accept expertnat clock signals 22/24, but still SD and no nice Controll App like with MPD)…

    • #1771
      The Well Audio
      Participant

      No, the DSD DAC board is not the Sonic Empire DAC.
      It’s an alternative to the DAC Lite we would like to try.
      After the comparison between the DAC Lite and the DSD DAC we will choice the ultimate way for the Sonic Empire DAC.

      Glad that the SdTrans now works.

    • #1799
      jmmbarco
      Participant

      Yes, our TWSAFB-RX is compliant with HDMI I2S Ps-Audio.

      DAC Lite plays up to 176/192 kHz with 5/6 MHz oscillators. And up to 384 kHz with 11/12 MHz oscillators.

      FIFO Lite does not perform any upsampling, so any upsample should be performed externally before driving the FIFO Lite.
      FIFO Lite accepts up to 384 kHz.

      DAC Lite has to be driven by the FIFO Lite, otherwise it does not work.
      It does not provide any oversampling, it’s a NOS DAC.
      It does not accept DSD, nor direct neither when driven by the FIFO Lite.

      There will be a DSD DAC board within 3-4 month. It will accept DSD only.

      Hi Andrea. Could you please share some details about the DSD dac?

      Will be using same 5/6(11/12) MHz oscillators? will it be driven by FIFO? and max sample rate?

       

      best

    • #1803
      The Well Audio
      Participant

      The TWSDAC-DSD will work with both 5/6 MHz and 11/12 MHz oscillators.

      With 5/6 MHz oscillators it plays DSD128 and with 11/12 MHz oscillators it plays DSD256.

      It will be driven by the FIFO Lite, we will provide the FPGA firmware update.
      It laso can driven by other source which provides balanced output since the DAC has balanced input.
      Anyway we cannot guarantee the same performance we will reach with the FIFO Lite, because the FIFO Lite drives directly the DAC with master clock, so directly from the oscillators. DATA are optically isolated from the master clock.

    • #1814
      Ivan
      Participant

      Hi Andrea,

      Can’t find info about TWSAFB-OI powering. Will it be OK to power it from FIFO’s (TWSAFB-LT) J27 3V3 output?

       

      Thnaks.

      Ivan.

    • #1815
      Ivan
      Participant

      And the second question.

      Seems like on your FIFO (TWSAFB-LT) there is no external xtal (clock) selection pin like it is realized on your separate TWTMC-STS-FSDO-S board. Is this means that I am forced to use another (separate) xtals/clocks for the I2S source as your FIFO is waiting for already formed I2S for proper clock freq recognition?

      Some explanation of my existing working scheme. In my existing DAC I do use your DRIXO clocks for generating/creating of the I2S from the very beginning. It works this way:

      BeagleBone Black (LAN-I2S endpoint, botic driver) sends the signal of 0 (44k) or 1 (48k) from the dedicated GPIO pins in accordance with the playing sampling rate (through my board with the isolator chip) to J7 header of your TWTMC-STS-FSDO-S. Your TWTMC-STS-FSDO-S switches between two clocks (45/49MHz) and sends the needed masterclock (through my board over the isolator chip) back to BBB. BBB creates the I2S from the incoming (correctly chosed) DRIXO masterclock and sends it to FIFO (and then to DAC).

      What is my point? I do not like situation when the initial I2S is formed from the other xtals/clocks that are worse than your DRIXO clocks. Will be sad to lost a possibility of a single clocking scheme for the whole chain from I2S initiation till the DAC tacting itself.

      My questions are relates to the upcoming order and I just want to be ready for your stuff will come some months later. Andrea what can you suggest in conjuction with the above described?

      Thank you!
      Ivan.

       

    • #1818
      The Well Audio
      Participant
      Ivan Said

      Hi Andrea,

      Can’t find info about TWSAFB-OI powering. Will it be OK to power it from FIFO’s (TWSAFB-LT) J27 3V3 output?

       

      Thnaks.

      Ivan.

      J27 is not a very clean power supply, we suggest to power the TWSAFB-OI with the same low noise regulator used to power the clock section of the FIFO Lite (J18).

      • #1822
        Ivan
        Participant

        Got it. Thx.

    • #1819
      The Well Audio
      Participant

      Ivan Said

      And the second question.

      Seems like on your FIFO (TWSAFB-LT) there is no external xtal (clock) selection pin like it is realized on your separate TWTMC-STS-FSDO-S board. Is this means that I am forced to use another (separate) xtals/clocks for the I2S source as your FIFO is waiting for already formed I2S for proper clock freq recognition?

      Some explanation of my existing working scheme. In my existing DAC I do use your DRIXO clocks for generating/creating of the I2S from the very beginning. It works this way:

      BeagleBone Black (LAN-I2S endpoint, botic driver) sends the signal of 0 (44k) or 1 (48k) from the dedicated GPIO pins in accordance with the playing sampling rate (through my board with the isolator chip) to J7 header of your TWTMC-STS-FSDO-S. Your TWTMC-STS-FSDO-S switches between two clocks (45/49MHz) and sends the needed masterclock (through my board over the isolator chip) back to BBB. BBB creates the I2S from the incoming (correctly chosed) DRIXO masterclock and sends it to FIFO (and then to DAC).

      What is my point? I do not like situation when the initial I2S is formed from the other xtals/clocks that are worse than your DRIXO clocks. Will be sad to lost a possibility of a single clocking scheme for the whole chain from I2S initiation till the DAC tacting itself.

      My questions are relates to the upcoming order and I just want to be ready for your stuff will come some months later. Andrea what can you suggest in conjuction with the above described?

      Thank you!
      Ivan.

       

      The FIFO Lite detects the I2S sample rate family and automatically selects the proper clock.

      If you want to drive the source with the same master clock of the FIFO you can simply get the MCK output from one of the u.fl connectors labelled MCK (J12 or J21).
      It comes from the external oscillators (DRIXO in your case), it’s already converted to square wave and it’s already selected by the I2S input sample rate family.

      • This reply was modified 1 month, 3 weeks ago by Moderator.
      • #1823
        Ivan
        Participant

        I think you do not understood. In my case the I2S is simply not exist untill I feeding the MCK to the BBB mck-in. Correct me if I wrong please.

        1) Your FIFO is waiting for an independant incoming I2S and only after its presence at I2S input the FIFO’ logic is analyzing this incoming I2S for freqs (by BCK or LRCK – I don’t know which line exactly) and compares it with two masterclocks of Xtals/DRIXOs. If the freqs of the incoming I2S are not in-sync with the first xtal, then FIFO’s logic is switching to second xtal.

        But what will be in my case? I see two scenarios.

        2) Your FIFO is waiting for incoming I2S and as a result do not generates MCK at all as BBB can’t make I2S without incoming MCK. Game over.

        3) Your FIFO is generating MCK randomly. Xtal1 for example or last previously used – I don’t know which exactly, but for clarity reason let it be 11.2896MHz (44k1 family rate).

        3a) I play music in 44k1 family rate, CDDA format. BBB generates the I2S at the “sonically correct speed”, your FIFO compares this incoming I2S with 11.2896MHz Xtal -> it is matching. Result: lucky case – everything is OK.

        3b) I play music in 48k, DVDA (96k) format. BBB generates the I2S at the “sonically incorrect speed”, but your FIFO compares this incoming I2S with 11.2896MHz Xtal and as a result do not recognizing that anything is wrong as the incoming I2S was created from this 11.2896MHz MCK. Result: Music plays at incorrect speed. Game over.

         

        The 3rd scenario is not a theory, but it is based on my existing situation (with Ian’s fifopi). I have solved this using your TWTMC-STS-FSDO-S board for proper MCK freq selection as BBB has a dedicated pins which sends 0 or 1 to your TWTMC-STS-FSDO-S board before starting playback (before generating I2S).

         

    • #1831
      The Well Audio
      Participant

      When the FIFO Lite starts the x48 oscillator family is selected.
      Moreover the FIFO Lite auto-performs oscillators selection when the I2S input signal is detected, and there is no way to manually select between the oscillators.

      So the only way could be using a pair of splitters after the oscillators (one for each oscillators) to send the MCK to both FIFO Lite and TWTMC-STS-FSDO-S boards.
      This way the FIFO Lite is fed by the MCK and the proper oscillator is selected, and also the BBB will receive the MCK by the TWTMC-STS-FSDO-S.

    • #1839
      Ivan
      Participant

      Moreover the FIFO Lite auto-performs oscillators selection when the I2S input signal is detected, and there is no way to manually select between the oscillators.

      Sad story.

      So the only way could be using a pair of splitters after the oscillators (one for each oscillators) to send the MCK to both FIFO Lite and TWTMC-STS-FSDO-S boards.
      This way the FIFO Lite is fed by the MCK and the proper oscillator is selected, and also the BBB will receive the MCK by the TWTMC-STS-FSDO-S.

      Adding another large board (like TWTMC-STS-FSDO-S) in addition to your FIFO board looks a bit overkilling decision, definitely unwanted entity.

      Nevertheless,
      Andrea, the main question actually is:

      Does the followed 2 connections scenarios are really equal in terms of I2S quality after your FIFO(+DRIXOs) ?

      1. Work with independantly formed I2S (made from a regular quality xtals/clocks like NDK’s NZ2520SDA or Accusillicon’s 318b)

      vs

      2. Work with I2S formed from the same DRIXO’s clocks as used for FIFO itself

       

      Answering to this question will help me to understand what is really better: simply to add a pair of a regular xtals on top of BBB (there is a project from Pavel Pogodin called PPY`s ReClocker here: puredsd.ru) for prepare an independant I2S before your FIFO for proper DRIXOs selection;

      or to follow the usage of an extra multiplexers and boards to make a solid syncing scheme from the I2S creating till its correction through your FIFO.

      Thank you!

      p.s. I think that second approach is more correct and really can’t understand why did you excluded the possibility of external (manual clock selection) as it was realized on a separate squarer FSDO board.

       

    • #1842
      The Well Audio
      Participant

      The FIFO Lite isolates the DAC from the source, since they work in separate time domains.

      So we suggest the first approach, DRIXO oscillators feed the FIFO Lite only.

      Finally, it’s a little complex to explain why the FIFO Lite does not accept external control of the clock selection. I should explain all the hardware and software architecture.
      What I can say is that without the auto-selection of the master clock the FIFO Lite cannot work, unless we redesign all this architecture.

    • #1844
      Ivan
      Participant

      What I can say is that without the auto-selection of the master clock the FIFO Lite cannot work, unless we redesign all this architecture.

      Sure Andrea. I just want to understand how to proceed.

      So we suggest the first approach, DRIXO oscillators feed the FIFO Lite only.

      OK. This means that I do not need to buy extra FSDO boards.

       

      Honestly… It is VERY HARD for me to believe that it is absolutely doesn’t matter how bad was the masterclock(s) during the I2S generatng/initiation before your FIFO(+DRIXOs). But OK, I think I will have enough DRIXO clocks to check there influence before FIFO. I will came back later with conclusions.

      Thanks for answers!

      Ivan.

       

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