Reply To: The Well synchronized asynchronous FIFO buffer – Slaved I2S reclocker

Forum Digital line The Well synchronized asynchronous FIFO buffer – Slaved I2S reclocker Reply To: The Well synchronized asynchronous FIFO buffer – Slaved I2S reclocker

#1823
Ivan
Participant

I think you do not understood. In my case the I2S is simply not exist untill I feeding the MCK to the BBB mck-in. Correct me if I wrong please.

1) Your FIFO is waiting for an independant incoming I2S and only after its presence at I2S input the FIFO’ logic is analyzing this incoming I2S for freqs (by BCK or LRCK – I don’t know which line exactly) and compares it with two masterclocks of Xtals/DRIXOs. If the freqs of the incoming I2S are not in-sync with the first xtal, then FIFO’s logic is switching to second xtal.

But what will be in my case? I see two scenarios.

2) Your FIFO is waiting for incoming I2S and as a result do not generates MCK at all as BBB can’t make I2S without incoming MCK. Game over.

3) Your FIFO is generating MCK randomly. Xtal1 for example or last previously used – I don’t know which exactly, but for clarity reason let it be 11.2896MHz (44k1 family rate).

3a) I play music in 44k1 family rate, CDDA format. BBB generates the I2S at the “sonically correct speed”, your FIFO compares this incoming I2S with 11.2896MHz Xtal -> it is matching. Result: lucky case – everything is OK.

3b) I play music in 48k, DVDA (96k) format. BBB generates the I2S at the “sonically incorrect speed”, but your FIFO compares this incoming I2S with 11.2896MHz Xtal and as a result do not recognizing that anything is wrong as the incoming I2S was created from this 11.2896MHz MCK. Result: Music plays at incorrect speed. Game over.

 

The 3rd scenario is not a theory, but it is based on my existing situation (with Ian’s fifopi). I have solved this using your TWTMC-STS-FSDO-S board for proper MCK freq selection as BBB has a dedicated pins which sends 0 or 1 to your TWTMC-STS-FSDO-S board before starting playback (before generating I2S).