Reply To: The Well synchronized asynchronous FIFO buffer – Slaved I2S reclocker

Forum Digital line The Well synchronized asynchronous FIFO buffer – Slaved I2S reclocker Reply To: The Well synchronized asynchronous FIFO buffer – Slaved I2S reclocker

#1839
Ivan
Participant

Moreover the FIFO Lite auto-performs oscillators selection when the I2S input signal is detected, and there is no way to manually select between the oscillators.

Sad story.

So the only way could be using a pair of splitters after the oscillators (one for each oscillators) to send the MCK to both FIFO Lite and TWTMC-STS-FSDO-S boards.
This way the FIFO Lite is fed by the MCK and the proper oscillator is selected, and also the BBB will receive the MCK by the TWTMC-STS-FSDO-S.

Adding another large board (like TWTMC-STS-FSDO-S) in addition to your FIFO board looks a bit overkilling decision, definitely unwanted entity.

Nevertheless,
Andrea, the main question actually is:

Does the followed 2 connections scenarios are really equal in terms of I2S quality after your FIFO(+DRIXOs) ?

1. Work with independantly formed I2S (made from a regular quality xtals/clocks like NDK’s NZ2520SDA or Accusillicon’s 318b)

vs

2. Work with I2S formed from the same DRIXO’s clocks as used for FIFO itself

 

Answering to this question will help me to understand what is really better: simply to add a pair of a regular xtals on top of BBB (there is a project from Pavel Pogodin called PPY`s ReClocker here: puredsd.ru) for prepare an independant I2S before your FIFO for proper DRIXOs selection;

or to follow the usage of an extra multiplexers and boards to make a solid syncing scheme from the I2S creating till its correction through your FIFO.

Thank you!

p.s. I think that second approach is more correct and really can’t understand why did you excluded the possibility of external (manual clock selection) as it was realized on a separate squarer FSDO board.