Reply To: The Well synchronized asynchronous FIFO buffer – Slaved I2S reclocker

Forum Digital line The Well synchronized asynchronous FIFO buffer – Slaved I2S reclocker Reply To: The Well synchronized asynchronous FIFO buffer – Slaved I2S reclocker

#1844
Ivan
Participant

What I can say is that without the auto-selection of the master clock the FIFO Lite cannot work, unless we redesign all this architecture.

Sure Andrea. I just want to understand how to proceed.

So we suggest the first approach, DRIXO oscillators feed the FIFO Lite only.

OK. This means that I do not need to buy extra FSDO boards.

 

Honestly… It is VERY HARD for me to believe that it is absolutely doesn’t matter how bad was the masterclock(s) during the I2S generatng/initiation before your FIFO(+DRIXOs). But OK, I think I will have enough DRIXO clocks to check there influence before FIFO. I will came back later with conclusions.

Thanks for answers!

Ivan.