Reply To: The Well synchronized asynchronous FIFO buffer – Slaved I2S reclocker

Forum Digital line The Well synchronized asynchronous FIFO buffer – Slaved I2S reclocker Reply To: The Well synchronized asynchronous FIFO buffer – Slaved I2S reclocker

#2030
The Well Audio
Participant

I2S output (input for the TDA1387) means continuous clock, so the clean side of the FIFO cannot be used.
You have to use the signals coming from the FPGA (BCK, DATA and WS) as showed by the Windows app.

The only way to improve the jitter is using the OIR board which performs the reclock of both BCK and WS (LRCK).