Reply To: The Well synchronized asynchronous FIFO buffer – Slaved I2S reclocker

Posted bynguyen phuong

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28/01/2023 at 10:54 #2069
nguyen phuong
Participant

    HI

    1. about FIFO setting: I connect pin I2S out on Ered Dock board to Port I2S1 in (on FIFO Lite) as follow

    – Pin 1, 3, 5, 7, 11 on Ered Dock (Ground) to Ground pin on  Port I2S1 in FIFO Lite BOARD

    – Pin 2 on Ered Dock (MCK)– MCK pin on  Port I2S1 in FIFO Lite BOARD

    – Pin 6 on Ered Dock (BCLK) — BCK pin on  Port I2S1 in FIFO Lite BOARD

    – Pin 8 on Ered Dock (PCM-LRCLK) — LRCLK pin on  Port I2S1 in FIFO Lite BOARD

    – Pin 12 on Ered Dock (PCM_SDATA/DSL) — DATA pin on  Port I2S1 in FIFO Lite BOARD

    (I send the table on pdf file insert, so that you can easily imagine)

     

    2.DAC that I chosen when I have configured the FIFO Lite ?. because the I2S out from board Transmitter I2S over HDMI then go in to another I2S on HDMI is diffenretial I2S, so may be we need not chose DAC ??

    Am I right or not ?  I”m not good in electronic, sorry.

    Tks

    Phương