Reply To: The Well synchronized asynchronous FIFO buffer – Slaved I2S reclocker

[The Well AudioParticipant]

I don’t know how Ered Dock outputs I2S.

I could assume:
– Ered-Dock pin 12 PCM_SDATA0/DSDL to FIFO Lite J14 pin 1 DATA
– Ered-Dock pin 13 Ground to FIFO Lite J14 pin 2 GND
– Ered-Dock pin 6 BCLK to FIFO Lite J14 pin 3 BCK
– Ered-Dock pin 7 Ground to FIFO Lite J14 pin 4 GND
– Ered-Dock pin 8 PCM_LRCLK to FIFO Lite J14 pin 5 LRCK
– Ered-Dock pin 9 Ground to FIFO Lite J14 pin 6 GND
– optional Ered-Dock pin 2 MCLK to FIFO Lite J14 pin 7 MCK
– Ered-Dock pin 3 Ground to FIFO Lite J14 pin 8 GND

I’m not sure because they listed SDATA0 and SDATA1 while I2S has DATA only (both channel alternating). I assume DATA0 because they specified “Stereo PCM audio data”.

Please, ask the manufacturer to confirm.