The problem is that SPDIF is a very jittery interface by itself, since the clock is embedded in data.
So that, there will be a PLL after the SPDIF receiver, which practically vanishes the help of the FIFO.
That’s the reason we have not implemented SPDIF output in the FIFO.
SPDIF will be an input for the FIFO, since in the future we will design a SPDIF-I2S interface, but not an output.
We like to be honest, so we cannot incourage such way, because the SPDIF shouln’t be used to get good performance.
About the tantalum nitride version of the DAC Lite I understand your frustration, but keep in mind that we cannot test all the ways when we develop a device. Developing cost are huge, so we have to make some design choices at the beginning.
We have discovered the TN resistors when we tested the DSD DAC because a user suggested to try them. Then we also have built a TN version of the DAC Lite.
It sounds a little more detailed with TN resistors, but it’s a small difference, the standard DAC Lite sounds already very well.
Hope you undertand.