Reply To: The Well synchronized asynchronous FIFO buffer – Slaved I2S reclocker

[hollowman]

hollowman Said

Hi All:

I was long-time Hollowman (and many aliases) on DIYA. Banned, there, of course for challenging the groupthink 😉

Kudos to andrea mori for creating this thewellaudio.com site/forum as an alternative to DIYA!

My main question is how the andrea mori FIFO project differs from the IANCANADA fifo project. I can’t find Ian’s schematics nor can I (of course) post on DIYA to enquire about specifics.

 

Follows some features you can get from our FIFO buffer but you cannot find in Iananada’s FIFO (in brackets):

Inputs: 4 x selectable I2S input (1 input)

Output format: compatible with almost all modern and old DACs (I2S/DSD DACs only, for PCM you need the I2S to PCM board)

Custom output format: for TDA1541A (offset binary), TWSDAC-LT DAC Lite, Soekris DAM1021 upgrade, AD5791, TDA1541A and AD1862 dual mono sign magnitude (not available)

Dither: 8 x selectable dither depth separately for each source (not available)

FIFO buffer depth: 8 x selectable buffer depth separately for each source, from 65kb to 8Mb (not available)

Optional: digital DAC calibration to reach the best precision, TWSDAC-LT DAC Lite and maybe other DACs (not available in DSD mode); Return to Zero logic for DSD output format (not available)

Configuration: all settings can be configured one time by USB connection to the Windows application (not available)

Master Clock selection: T-switch configuration relais to select the sample rate family instead of multiplexers (multiplexers)

Optical isolation: MCK and LRCK optical isolated from the FPGA and the micro to avoid interferences (RF isolation)

External Master Clock: SMA connectors for external clocks with sine to square converter on board (you have to add SinePI to convert from sine to square)

Direct clock output: LRCK directly from the MCK (optical isolation) instead of from the FPGA (not avalable)

Phase noise: very low phase noise outputs (higher phase noise as measured)